Low Temperature Low Pressure Metal – Metal Bonding Technology: Towards Package less, Wafer scale Heterogeneous Integration

Bonam, Satish and Singh, Shiv Govind (2020) Low Temperature Low Pressure Metal – Metal Bonding Technology: Towards Package less, Wafer scale Heterogeneous Integration. PhD thesis, Indian Institute of Technology Hyderabad.

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Abstract

Continuous scaling of transistor physical dimensions led to the tremendous growth in semiconductor industry and it became the pivot for the communication revolution that we are witnessing. Billions of transistors were integrated in the area of fingertip in accordance with the observation by Gordon Moore, famously known as Moore’s law. In the process of transistor scaling, the complexity involved in interconnecting billions of transistors led to the usage of multilayer metal stack which in turn increased the interconnect delay. These long interconnects has become the limitation as they have become the primary source of parasitics. Inherent RC delay caused by these wires has become a bottleneck so much so that scaling down further may not improve the overall system performance unless or until the long interconnect problem is resolved. Keeping this in view, the focus shifted towards developing a new integration architecture that reduces the interconnect delays and allowing higher density of transistors in smaller footprint. 3D Integration is one of the best integration technology where processed wafers/chips are stacked vertically and the longer interconnects are replaced by shorter interconnects. This can be realized by incorporating silicon vias which requires via etching and via filling. Among several advantages, one of the major advantages of 3D IC integration is the integration of complete system where different functional blocks with different processes can be integrated in one platform, thus enabling the enticing concept of heterogeneous integration. Realization of 3D integration requires stacking/interconnecting the wafers/chips in Z-direction (3rd dimension) with help of bonding. Among the various bonding techniques that have been proposed for realizing the 3D stacking, thermo-compression bonding is an attractive choice as it ensures interconnection between two wafers via metal layer along with high mechanical stability. In this method, two wafers can be bonded by simultaneous application of suitable force and temperature. Conventionally, Cu has been used as an intermediate bonding metal owing to its higher electrical and thermal conductivity values and higher electro-migration resistance as compared to that of Al. Thermo compression bonding is also named as diffusion bonding, where metal atoms diffuses from one surface to another surface to form continuous grain growth across the interface between two mated surfaces. In Cu-Cu thermo compression bonding, the diffusion of Cu atoms is hampered by its oxidation. To nullify copper oxide presence, higher temperatures are required which is detrimental to the already fabricated devices beneath. Apart from surface oxidation, surface roughness is also a critical factor in bonding. An increase in surface roughness reduces the bond strength and also results in the formation of voids due to uneven contact between the two surfaces during bonding. Uneven contact plays a vital role for requirement of high pressure during bonding but high pressure is not suitable for CMOS applications. Hence preventing surface oxidation, inhibiting surface contamination and ensuring low surface roughness are major requirements for achieving low temperature and low pressure Cu-Cu thermo-compression bonding. In this regard, we have demonstrated low temperature and pressure wafer on wafer (WoW) Cu-Cu thermos compression bonding using ultra-thin gold (Au, Noble material) passivation layer, optimized for desirable surface smoothness along with proper passivation and smaller Cu diffusion time. Au is a promising candidate for passivation, as it does not form a native oxide layer on its surface on exposure to air. Also, it offers significantly high resistance to surface oxidation as compared to the previously used Ti passivation. Furthermore, gold is extensively used in die bonding concerning packaging applications and also damascene process compatible. In addition, gold is used in MEMS encapsulation and hermitical sealing of MEMS devices. Also, it is reported that thicker film of Au can be deposited and can be polished to desired thickness using chemical mechanical polishing. Keeping these in view, herein, we report thermo-compression Cu-Cu bonding with an ultra-thin gold passivation layer. The passivation layer thickness has been experimentally optimized to attain optimum performance. With a passivation layer thickness of 3 nm, we have achieved Cu-Cu bonding at low temperature (140 °C) and low pressure (0.33 MPa). Traditionally Micro-strip patch antenna(MPA) are fabricated on low dielectric constant substrates like Duroid, FR4 to increase the radiation efficiency. These Antennas requires bond wires to connect to Integrated circuits(ICs). But, the bond wires will result lot of parasitics and power losses especially at higher frequencies. An on chip antenna can ease the requirement of bond wires between antenna and IC and increase total system performance and reliability. But, the fabrication on of an On chip antenna on silicon substrate suffers by its high dielectric constant (Ɛr=11.7) and its conductive losses. This thesis also reports the fabrication of Aperture coupled 3D on chip silicon patch using low temperature, low pressure Cu-Cu thermos-compression bonding. This is the first demonstration of translating post CMOS compatible vertical integration process technology into a practical device application. The proposed fabrication process flow not only utilizes Cu for bonding/stacking but also adapts this metallic interlayer as the common ground. Fabrication methods and bonding conditions were optimized to yield the best result. The on-chip antenna exhibited a resonance frequency at 13.4 GHz with VSWR 1.16. This technology is the way forward for fabricating, miniaturized, high performance on-chip antennas. We believe this practical demonstration of a device using Cu-Cu low temperature, low pressure thermo-compression bonding would lead to several similar kinds of devices and architectures in the near future paving the way for package less, wafer scale heterogeneous integration

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