A Single-Phase 5-Level Inverter Topology with Reduced Semiconductor Switches

Janaki Ramaiah, V and Siva kumar, K (2018) A Single-Phase 5-Level Inverter Topology with Reduced Semiconductor Switches. In: 8th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES, 18- 21 December 2018, Chennai, India.

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Abstract

For any switching frequency, multilevel inverters produce better harmonic profile compared to basic 2-level inverters. Among the available multilevel inverters topologies in the literature, some of the topologies like neutral point clamped (NPC) or diode clamped, flying capacitor (FC) or capacitor clamped, and H-bridge are conventionally used. However, the NPC and FC type inverter topologies comprises the capacitor voltage balancing issue, and the H-bridge requires more number of isolated DC voltage sources and semiconductor switches. To overcome the issues encountered with the conventional topologies, a new single-phase 5-level inverter topology by excluding the capacitor components and with a reduced number of semiconductor switches is proposed in this paper. A reduced number of levels is also achieved with the proposed topology under certain fault conditions.

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