Numerical device simulations of ionizing radiation effects on CMOS logic device performance

Bhukya, Sardar and Nayak, Kaushik (2018) Numerical device simulations of ionizing radiation effects on CMOS logic device performance. Masters thesis, Indian Institute of Technology Hyderabad.

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Abstract

This thesis work presents the numerical device analysis of ionizing radiation induced single-event e�ects (SEE) in CMOS logic devices in sub-130 nm technologies. The ionizing radiation (UV, X rays, gamma rays, swift heavy ions, cosmic rays) exposure in extreme space environment conditions can cause deleterious e�ects in microelectronic devices, such as total ionization dose (TID), SEE, crystal defects and other reliability concerns. This imposes the requirement that the electronic devices should be engineered to be radiation hardened. The initial thesis work involved the literature survey and review of the ionizing radiation characteristics, and their interaction with matter, e.g. photoelectric e�ect, compton e�ect, and pair production etc. Further, in the literature review, the mean energy loss of swift heavy ions traversing matter was studied using Bathe formula. In the thesis stage-1 work, the room temperature numerical device simulations of two dimen- sional planar 100 nm n- and p-MOSFETs were carried out following Drift-Di�usion (DD) transport formalism. The steay-state DC simulations were performed to obtain the terminal characteristics. Further in stage-2 work, mixed-mode simulations were carried out using DD transport, in order to predict CMOS inverter voltage transfer characteristics (VTC) and CMOS NAND and NOR gate characteristics. The e�ect of TID on MOSFET characteristics were investigated. The single event transients (SET) in CMOS inverter due to ionizing radiation exposure, is further simulated to study the e�ects of momentary voltage spikes at output circuit node. The e�ect of SET on the three stage fan-out 1 Ring Oscillator (RO) transient characteristics and stage delay were numerically analyzed. In the �nal stage of the thesis work, another SEE known as single event upset (SEU) was simulated within the mixed-mode simulation framework to predict its e�ect on six-transistor(6T) SRAM cell static memory operation (VTC), read and write operations. The SEE in combinational is SET and in sequential circuit it is SEU. The SET becomes SEU in memory elements. This e�ects has been investigated in Conventional 6T SRAM cell, which uses bi-stable latching circuitry made of Transistors/MOSFETS to store each bit. The conventional 6T memory cell comprised of two CMOS inverters cross coupled with two pass transistors connected to a complimentary bit lines. Read and Write operations along with VTCs during both operations were simulated. The e�ect of heavy ion during write operation was investigated and simulated to see the SEU impact in memory devices. The occurrence of SETs and the propensity for propagation is enhanced as geometric dimension and capacitance scale down, while the probability of SET capture grows with increasing circuit operational frequency. The logic gates with small dimension transistors are particularly sensitive to SETs. So, there is a need to see these e�ects in small scale devices as well. For that purpose, we have calibrated the CMOS 45nm technology. As the short channel devices are going to be the future of semiconductor industry, this work can be continued in future on short channel devices to design a rad-hardened device e�ectively and e�ciently.

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