A low/high band highly linearized reconfigurable down conversion mixer in 65nm CMOS process

Gupta, N and Dutta, Asudeb and Singh, Shiv Govind (2015) A low/high band highly linearized reconfigurable down conversion mixer in 65nm CMOS process. In: Nordic Circuits Systems Conference (NORCAS): NORCHIP & International Symposium on System Chip (SoC), OCT 26-28, 2015, Oslo, NORWAY.

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Abstract

This paper presents a universal down conversion mixer for a multistandard wireless receiver with adapted reconfigurability in the form of RF bandwidth, active/passive and IF bandwidth. In the proposed architecture RF bandwidth reconfigurability is reconfigured between low band (LB) RF frequency and high band (HB) RF frequency mixer modes. LB / HB reconfigurability is made through power switching the transconductance amplifier. Active / Passive reconfigurability is made through switching the input signal between gate and source terminal of input transistors and enabling/disabling the transimpedance stage at the output. The CMOS transmission gate (TG) switches are designed to provide optimum headroom in this low voltage design. The proposed circuit is designed in the UMC 65nm RFCMOS technology with 1.2V supply voltage. From the simulation results, the proposed circuit shows conversion gain of 22/26 dB and 25/31 dB, noise figure of 14.2/12.1 dB and 11.5/8.16 dB, IIP3 of 10/8.1 dBm and 6.4/3 dBm in LB and HB respectively where all these figures suggest passive/active mode. Hence this circuit will be much helpful in multi-standard receiver design.

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