1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture

Purushothama Chary, P and Peerla, Rizwan Shaik and Regulagadda, Sesha Sairam and Naseeb, Mohd Abdul and Acharyya, Amit and P, Rajalakshmi and Mandal, Debashis and Dutta, Asudeb (2015) 1.2 mW 2.4 GHz PLL for ZigBee and BLE standard in single-well 0.18 µm CMOS with efficient divider architecture. In: Asian Pacific Conference on Postgraduate Research In Microelectronics And Electronics (PRIMEASIA), Nov 27-29, 2015, Vasavi Coll Engn, Hyderabad, India.

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Abstract

This paper proposes a novel single-well VCO in PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs PMOS based charge recycling technique in Voltage Controlled Oscillator (VCO) and a Current Mode Logic (CML) divider for I-Q generation in single-well CMOS. An efficient, low current, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The VCO-CML cell gives phase noise of -147 dBc/Hz at 1 MHz offset. PLL consumes 1.2mW of power at 1.2V supply with a settling time less than 45 mu s and core area is 743 m x 416 mu m using UMC 0.18 m CMOS Mixed Mode Technology.

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