A Robust Reliable and Low Complexity on Chip f-QRS Detection and Identification Architecture for Remote Personalized Health Care Applications

Vemishetty, N and Jain, A and Amber, A and Maheshwari, S and Jagirdar, A and Acharyya, Amit (2015) A Robust Reliable and Low Complexity on Chip f-QRS Detection and Identification Architecture for Remote Personalized Health Care Applications. Journal of Low Power Electronics, 11 (3). pp. 387-400. ISSN 1546-1998

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Abstract

With increasing number of cardiovascular cases throughout the world, personalized remote healthcare has emerged as a solution to the constraints encountered by pervasive and affordable healthcare from both comfort and economic perspectives. Personalized healthcare applications, generally involve battery operated devices which form a part of Internet-of-Things (IoT) or Cyber-physical systems (CPS), where power becomes a major bottleneck. With this motivation, we present a novel low-complexity on-chip architectural implementation of our recently proposed algorithm for automated detection and identification of fragmentation in QRS complex of standard 12-lead ECG signals. The proposed architecture also identifies the morphology of frag mented QRS viz. Notched S, RsR' without elevation, rsR' and many other. QRS complexes were extracted using our recently proposed Hybrid Feature Extraction Algorithm (HEFA). The proposed algorithm applies discrete wavelet transform using haar wavelet on the QRS complex to identify the position of occurrence of discontinuities/extrema and lays out classification rules for various types of fragmentation documented in the literature. Haar wavelet was chosen because of its enhanced time-resolution, accurate discontinuity detection properties. Its moving average nature allows simple hardware implementation. The verification of results of the architecture has been performed using 100 patients from MIT-BIH database and PhysioNet PTB database and their ECG were examined by two experienced cardiologists individually and the results were compared with those obtained from the architecture output, wherein we have achieved 95% diagnostic matching. The design has been implemented in 130 nm technology and operated at 1 MHz with V dd 1.3 V. The power consumption and area were found to be 22.4 μW and 0.22 mm2 respectively.

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