TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks

Das, Shirshendu (2023) TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks. Journal of Systems Architecture, 135. p. 102805. ISSN 1383-7621

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Abstract

Contemporary computing employs cache hierarchy to fill the speed gap between processors and main memories. In order to optimise system performance, Last Level Caches (LLC) are shared among all the cores. Cache sharing has made them an attractive surface for cross-core timing channel attacks. In these attacks, an attacker running on another core can exploit the access timing of the victim process to infiltrate the secret information. One such attack is called a cross-core Covert Channel Attack (CCA). Timely detection and then prevention of cross-core CCA is critical for maintaining the integrity and security of users, especially in a shared computing environment. In this work, we have proposed an efficient cross-core CCA mitigation technique. We propose a way-wise cache partitioning on targeted sets, only for the processes suspected to be attackers. In this way, the performance impact on the entire LLC is minimised, and benign applications can utilise the LLC to its full capacity. We have used a cycle-accurate simulator (gem5) to analyse the performance of the proposed method and its security effectiveness. It has been successful in abolishing the cross-core covert timing channel attack with no significant performance impact on benign applications. It causes 23% less cache misses in comparison to existing partitioning based solutions while requiring ≈0.26% storage overhead.

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IITH Creators:

IITH Creators	ORCiD
Das, Shirshendu	http://www.orcid.org/0000-0002-9232-4306

Item Type:

Article

Uncontrolled Keywords:

Cache partitioning; Cache security; Covert Channel Attack (CCA); Last level cache (LLC); Timing channel attacks; Cache hierarchies; Cache partitioning; Cache security; Covert channel attack; Covert channels; Last level cache; Last-level caches; Performance impact; Timing channel attack; Timing channels; Cache memory; Timing circuits

Subjects:

Computer science

Divisions:

Department of Computer Science & Engineering

Depositing User:

Mr Nigam Prasad Bisoyi

Date Deposited:

22 Aug 2023 05:35

Last Modified:

22 Aug 2023 05:35

URI:

http://raiithold.iith.ac.in/id/eprint/11591