Efficient in-plane nanomagnetic non-majority logic gate based arithmetic computation

Sivasubramani, Santhosh (2020) Efficient in-plane nanomagnetic non-majority logic gate based arithmetic computation. In: Spintronics XIII 2020, 24 August 2020through 4 September 2020, Virtual, Online.

Full text not available from this repository. (Request a copy)

Abstract

Nanomagnetic Logic (NML) based computation started emerging as a key alternative towards the Beyond CMOS based Rebooting Computing paradigm. Arithmetic computation using this NML can be performed using majority (based on the principles of Magnetic Quantum-dot Cellular Automata) and non-majority logic gates. However there have been extensive studies on the majority logic gates based NML arithmetic architectures, its counterpart needs extensive analysis. Kurtz et al., and Varga et al., have performed the pioneering work in designing non- majority based 'AND', 'OR' operations. Here in this study, we introduce the non-majority voting gate based half-subtractor and adder architecture design methodology. To the best of author's knowledge this is the first time demonstration of arithmetic nanomagnetic implementation using non-majority gate. Subsequently, it can be inferred from the micromagnetic simulations and modeling that an asymmetrically shaped nanomagnet can be used as a compute nanomagnet in performing computation. The results show that only 4 nanomagnets are required to perform half subtractor/adder leading to area efficient design. This reduction is achieved by exploiting the principles of SP hybrid anisotropy and Boolean optimizations. Thus it can be observed that the non-majority voting based computation can lead to area efficient nanomagnetic arithmetic architecture design. Consequently, the thermal bit-stability analysis has also been carried out for the proposed sub-5o nm design. © 2020 SPIE.

[error in script]

IITH Creators:

IITH Creators	ORCiD

Item Type:

Conference or Workshop Item (Paper)

Additional Information:

S.S. acknowledges the Institute Post Doctoral Fellowship from IIT Hyderabad and also would like to acknowledge the support from Dr. Amit Acharyya and computational support from AESICD Lab.

Uncontrolled Keywords:

Area Effcient Design; Arithmetic Computation; MQCA; Nanomagnetic Logic; Nanomagnetics; Non-Majority Gate; Novel Information Processing; Spintronics; Sub-50nm Design Methodology; Unconventional Architecture Design

Subjects:

Electrical Engineering

Divisions:

Department of Electrical Engineering

Depositing User:

. LibTrainee 2021

Date Deposited:

02 Nov 2022 09:05

Last Modified:

02 Nov 2022 09:05

URI:

http://raiithold.iith.ac.in/id/eprint/11130