A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes

Bhattacharjee, Indranil and Chowdary, Gajendranath (2022) A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 30 (9). pp. 1281-1293. ISSN 1063-8210

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Abstract

A picowatt programmable CMOS-based voltage reference (VR) for wireless sensor nodes (WSNs) is proposed in this work. It uses a pMOS current source and an nMOS current sink to generate a temperature-independent output voltage. A body bias potential is used to control the threshold voltage of the nMOS current sink to generate programmable output voltage. The architecture can achieve temperature compensated reference voltages for different temperature characteristics of body bias with the help of digital trimming. The body bias is generated on-chip using a dedicated body bias generation block. The prototype circuit is fabricated in the 0.18-μm CMOS process with deep-n-well (DNW) and occupies a total area of 0.022 mm2 including the body bias block and a 10-pF decoupling MIM capacitor. The circuit provides output voltages from 250 to 370 mV. A total of ten chips from two different wafers (five chips per wafer) were measured. The average temperature coefficient (TC) is measured to be 72.17 ppm/°C over -40°C to 80°C for a reference voltage of 349.7 mV. The average line sensitivity (LS) obtained is 0.093%/V with a power supply rejection (PSR) of -39 dB at 100 Hz. © 1993-2012 IEEE.

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