Pushkar, Dasika and Nayak, Kaushik
(2018)
Modeling and Simulation of Negative Capacitance
MOSFETs.
Masters thesis, Indian Institute of Technology Hyderabad.
Abstract
The current and voltage characteristics of a MOSFET device are maily characterized by the source
to channel barrier which is controlled by the gate voltage. The Boltazmann statistics which govern
the number of carriers that are able to cross the barrier indicates that to increase the current by a
decade, atleast 60 mV of rise in gate voltage is required. As a result of this limitation, the threshold
voltage of modern MOSFETs cannot be less than about 0.3 V for an ION to IOFF ratio of 5 decades.
This has put a fundamental bottleneck in voltage downscaling increasing the power consumption in
modern IC based chips with billions of transistors.
Sayeef Salahuddin and Supriyo Dutta proposed the idea of including ferroelectric in MOSFET
gate stack which allows an internal voltage ampli�cation at the MOSFET channel which can be used
to achieve a smaller subthreshold swing which would further reduce the power consumption of the
devices. In this thesis we have undertaken a simulation based study of such devices to study how
the inclusion of negative capacitance ferroelectrics leads changes in various device characteristics.
Initially we have taken a compact modeling based approach to study device characteristics in
latest industry standard FinFET devices. For this purpose we have used the BSIM-CMG Verilog A
model and modi�ed the model appropriately to include the e�ect of negative capacitance ferroelectric
in the gate stack. This simulation allowed us to observe that negative capacitance (NC) devices can
indeed give a subthreshold swing lesser than 60 mV/dec. Further other interesting properties like
negative output resistance and drain induced barrier rising are observed.
Using the compact models developed above, we have analyzed some simple circuits with NC
devices. Initially an inverter shows a hysteresis in the transfer characteristics. This can be attributed
to negative di�erential resistance. Ring oscillator analysis shows that RO frequency for NC devices
is lesser than that of regular devices due to enhanced gate capacitance and slower response of
ferroelectrics.
Scaling analysis has been performed to see the performance of NC devices in future technologies.
For this we used TCAD analysis coupled with Landau Khalatnikov equation. This analysis shows
that NC devices are more e�ective in suppressing short channel e�ects like DIBL and can hence be
used for further downscaling of the devices.
Finally we develop models to take into account the multidomain Landau equations for ferroelec-
tric into account. We have performed such an analysis for a ferroelectric resistor series network. A
similar analysis is performed for short channel double gate MOSFET without inter layer metal be-
tween ferroelectric and the internal MOS device. This analysis showed that coupling factor between
ferroelectric domains plays an important role in the device characteristics.
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