Study of gate current in advanced MOS architectures

Gauhar, G.A. and Chenchety, A. and Badami, O (2022) Study of gate current in advanced MOS architectures. Solid-State Electronics, 194. pp. 1-4. ISSN 0038-1101

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Abstract

We have carried out a comprehensive study of the gate current (IG) in advanced MOS architectures for different gate lengths and cross-section areas using an in–house simulation tool. We have considered only direct tunneling under the assumption that trap concentration and therefore the trap assisted current would be small in a matured technology. We have also studied the impact of the interfacial (IL) SiO2 layer on the gate current in the high-κ gate stack. Our results suggest that IL leads to an increase in the gate current for equivalent EOT. They also highlight that reduction in the cross-section area leads to a significant increase in the IG. © 2022 Elsevier Ltd.

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IITH Creators:	IITH Creators ORCiD Badami, O UNSPECIFIED
Item Type:	Article
Uncontrolled Keywords:	Gate current, Tunneling, WKB Approximation
Subjects:	Electrical Engineering
Divisions:	Department of Electrical Engineering
Depositing User:	. LibTrainee 2021
Date Deposited:	20 Jun 2022 11:24
Last Modified:	20 Jun 2022 12:00
URI:	http://raiithold.iith.ac.in/id/eprint/9323
Publisher URL:	https://doi.org/10.1016/j.sse.2022.108345
OA policy:	https://v2.sherpa.ac.uk/id/publication/4706
Related URLs:	Author

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