Venkateswarlu, Sankatali and Nayak, Kaushik
(2020)
Hetero-Interfacial Thermal Resistance Effects on Device Performance of Stacked Gate-All-Around Nanosheet FET.
IEEE Transactions on Electron Devices, 67 (10).
pp. 4493-4499.
ISSN 0018-9383
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Abstract
This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron-phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.
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