Low Complexity VLSI Architecture Design Methodology for Wigner Ville Distribution

Mopuri, Suresh and Acharyya, Amit (2020) Low Complexity VLSI Architecture Design Methodology for Wigner Ville Distribution. IEEE Transactions on Circuits and Systems II: Express Briefs, 67 (12). pp. 3532-3536. ISSN 1549-7747

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Abstract

In this brief, we propose a low complexity VLSI architecture design Methodology for Wigner Ville Distribution (WVD) computation. The proposed methodology performs both auto and cross WVD computations using only the half number of Fast Fourier transform (FFT) computations as opposed to the state of the art methodologies. The FPGA implementation for proposed methodology was performed for 16 bit fixed point and 32 bit single precision floating point numbers on the Xilinx Virtex-7 FPGA (XC7vx485tffg). The proposed methodology saves 49% energy consumption when compared with the state of the art methodology. However it can be noted that the proposed methodology is independent of the VLSI implementation platform and technology node.

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IITH Creators:

IITH Creators	ORCiD
Mopuri, Suresh	UNSPECIFIED
Acharyya, Amit	http://orcid.org/0000-0002-5636-0676

Item Type:

Article

Uncontrolled Keywords:

Fixed points; FPGA implementations; Single precision; State of the art; Technology nodes; VLSI architectures; VLSI implementation; WignerVille distribution (WVD)

Subjects:

Electrical Engineering

Divisions:

Department of Electrical Engineering

Depositing User:

. LibTrainee 2021

Date Deposited:

22 Jun 2021 04:27

Last Modified:

22 Jun 2021 04:27

URI:

http://raiithold.iith.ac.in/id/eprint/7972