Interface Analysis of High Reliable Hermitic Sealed Microfluidic Channels for Thermal Cooling in 3D ICs

Cheemalamarri, Hemanth Kumar and Bonam, Satish and Banik, Dhiman and Vanjari, Siva Rama Krishna and Singh, Shiv Govind (2019) Interface Analysis of High Reliable Hermitic Sealed Microfluidic Channels for Thermal Cooling in 3D ICs. In: 2019 IEEE 21st Electronics Packaging Technology Conference, EPTC 2019, 4-6 December 2019, Singapore.

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Abstract

Thermal management is the critical issue in all present conventional 2D electronic packages, and is more crucial in the case staked dies of advanced 3D IC technology, because of increased power density and complex chip designs. The traditional methods are reaching their limits towards cooling requirement of 3D ICs. The liquid cooling micro-channel are the most attractive for high heat flux mitigation. However, the integration of such micro-channels across the stacked dies, is challenging. In this work, we are proposing a facile method of fabrication and integration of a high reliable, tight sealed inter-die microfluidic channels for 3D ICs. The integration of inter-die microchannel over three stacked layers has been developed with titanium silicide as a bonding interface by simultaneous application of optimal heat and force is matching towards CMOS compatibility. Here, we demonstrated the reaction mechanism of titanium (Ti) and importance of Ti thickness across the bonding interface. The temperature and load optimizations carried out using the surface profile of Ti using AFM before bonding, and interface inspection after bonding, by using, C-SAM and razorblade insertion. The interface reactions and thickness of Ti optimization has inspected using X-FESEM and EDS profile. After conforming void free high reliable bonding interface, at optimized conditions, we fabricated fine pitch (200 μ m) with 100 μm width and 40 μm depth micro-channels at inter-dies of three-layer stacked silicon structure using titanium as interlayer. Along with, we demonstrated the micro channel integration across the stacked wafers for future high performance 3D IC designs in a facile approach.

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