Gupta, N and Dutta, Asudeb
(2018)
HIGH PERFORMANCE CMOS WIDE-BAND
RF FRONT-END WITH SUBTHRESHOLD
OUT OF BAND SENSING.
PhD thesis, Indian institute of technology Hyderabad.
Abstract
In future, the radar/satellite wireless communication devices must support multiple standards
and should be designed in the form of system-on-chip (SoC) so that a significant reduction
happen on cost, area, pins, and power etc. However, in such device, the design of a fully
on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously
becomes a multifold complex problem. Further, the inherent high-power out-of-band
(OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate
the receiver. Therefore, the proper blocker rejection techniques need to be incorporated.
The primary focus of this research work is the development of a CMOS high-performance low
noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further,
the various reconfigurable mixer architectures are proposed for performance adaptability of a
wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced
fully differential receiver is proposed. The receiver composed of a composite transistor
pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor
amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based
tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture
in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver
system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides
a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB
having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured
receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm,
occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary
subthreshold receiver is proposed to estimate the out of blocker power. As a redundant
block in the system, the cost and power minimization of the auxiliary receiver are achieved
via subthreshold circuit design techniques and implementing the design in higher technology
node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the
noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power
consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver
and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various
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reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance
according to the requirement of the selected communication standard. The down conversion mixers
configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth
reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept,
the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured
result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of
-11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW
and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz
for active/passive case respectively.
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