A low hardware complexity time domain quantizer for wideband multibit - ADCs

Jha, P and Patra, Pravanjan and Dutta, Asudeb (2015) A low hardware complexity time domain quantizer for wideband multibit - ADCs. In: IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Nov 27-29, 2015, Vasavi Coll Engn, Hyderabad, INDIA.

Preview

Text PrimeAsia_104-109_2015.pdf - Accepted Version Download (1MB) | Preview

Abstract

This paper presents proof of concept of a low hardware complexity time domain quantizer (TDQ) for wideband multibit countinuous time (CT) ΣΔ ADCs. Besides rendering multi-level quantization of the input signal, the proposed scheme generates a two-level loop feedback signal for the modulator. The two-level feedback eliminates the errors emanating from component mismatches in the feedback digital-to-analog converter (DAC) due to process variations. The complete scheme is modeled using Simulink (MATLAB) and is validated through simulation. A 2nd order ΣΔ modulator incorporating the proposed TDQ achieves a dynamic range of 45.7 dB for a bandwidth of 10 MHz and an input sine-wave of -5.78 dBFS amplitude.

[error in script]

IITH Creators:	IITH Creators ORCiD Dutta, Asudeb UNSPECIFIED
Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	TO-DIGITAL CONVERTER; VOLTAGE-CONTROLLED OSCILLATOR; A/D CONVERTER; DESIGN; CMOS; MODULATORS; MM(2); BANDWIDTH
Subjects:	Others > Electricity
Divisions:	Department of Electrical Engineering
Depositing User:	Team Library
Date Deposited:	22 Aug 2016 04:40
Last Modified:	31 Jul 2018 06:53
URI:	http://raiithold.iith.ac.in/id/eprint/2660
Publisher URL:	https://doi.org/10.1109/PrimeAsia.2015.7450479
Related URLs:	Google Scholar

Actions (login required)

View Item

Statistics for this ePrint Item