Stress analysis in 3D IC having Thermal Through Silicon Vias (TTSV)

Patel, S B and Ghosh, T and Dutta, Asudeb and Singh, Shiv Govind (2013) Stress analysis in 3D IC having Thermal Through Silicon Vias (TTSV). In: 63rd Electronic Components and Technology Conference (ECTC), 28-31 May 2013, Las Vegas, NV.

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Abstract

TTSV is proposed for the removal of heat from between the IC layers as these TTSVs carries heat down to the sink. However, it may generate stress in Silicon. In the present paper, thermal-stress simulation of stack consists of three IC layers bonded face up is performed using finite element modeling tools. We also analyzed the stress generated in 3D IC containing TTSV. Further we proposed a method for lower stress around the TTSV. The method proposed decreases the Von Misses Stress by a value of 40Mpa on average considering all the IC layers. Thus by achieving this, functionality of the chip becomes more reliable.

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IITH Creators:	IITH Creators ORCiD Dutta, Asudeb UNSPECIFIED Singh, Shiv Govind http://orcid.org/0000-0001-7319-879X
Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	3D IC, CNT (Carbon Nano Tube), CVD Diamond, TTSV
Subjects:	Others > Engineering technology
Divisions:	Department of Electrical Engineering
Depositing User:	Library Staff
Date Deposited:	24 Feb 2016 05:56
Last Modified:	11 Sep 2017 09:58
URI:	http://raiithold.iith.ac.in/id/eprint/2211
Publisher URL:	https://doi.org/10.1109/ECTC.2013.6575910
Related URLs:	Google Scholar

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