DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing

Potluri, S and A, Satya Trinadh and Ch, Sobhan Babu and Kamakoti, V and Chandrachoodan, N (2015) DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. Transactions on Design Automation of Electronic Systems, 21 (1). 14:1-14:25. ISSN 1084-4309

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Abstract

Scan-based testing is crucial to ensuring correct functioning of chips. In this scheme, the scan and capture phases are interleaved. It is well known that for large designs, excessive switching activity during the launch-to-capture window leads to high voltage droop on the power grid, ultimately resulting in false delay failures during at-speed test. This article proposes a new design-for-testability (DFT) scheme for launch-on-shift (LOS) testing, which ensures that the combinational logic remains undisturbed between the interleaved capture phases, providing computer-aided-design (CAD) tools with extra search space for minimizing launch-to-capture switching activity through test pattern ordering (TPO). We further propose a new TPO algorithm that keeps track of the don't cares during the ordering process, so that the don't care filling step after the ordering process yields a better reduction in launch-to-capture switching activity compared to any other technique in the literature. The proposed DFT-assisted technique, when applied to circuits in ITC99 benchmark suite, produces an average reduction of 17.68% in peak launch-to-capture switching activity (CSA) compared to the best known lowpower TPO technique. Even for circuits whose test cubes are not rich in don't care bits, the proposed technique produces an average reduction of 15% in peak CSA, while for the circuits with test cubes rich in don't care bits (≥75%), the average reduction is 24%. The proposed technique also reduces the average power dissipation (considering both scan cells and combinational logic) during the scan phase by about 43.5% on an average, compared to the adjacent filling technique.

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IITH Creators:

IITH Creators	ORCiD
Ch, Sobhan Babu	UNSPECIFIED

Item Type:

Article

Additional Information:

The authors would like to thank Dr. V. R. Devanathan from Texas Instruments, Bangalore, and Ananth Hari from Embedded Systems Lab, IIT Madras, for the useful discussions.

Uncontrolled Keywords:

Design, Algorithms, Reliability, Digital systems testing, peak launch-to-capture switching activity, scan flip-flop, C-element, X-filling, critical path matching

Subjects:

Computer science > Big Data Analytics

Depositing User:

Team Library

Date Deposited:

14 Dec 2015 09:32

Last Modified:

14 Dec 2015 09:32

URI:

http://raiithold.iith.ac.in/id/eprint/2075

Publisher URL:

http://dx.doi.org/10.1145/2790297