Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate

Haldar, Arabinda and Murapaka, Chandrasekhar and Acharyya, Amit (2023) Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate. Nanotechnology, 34 (13). 13LT01. ISSN 0957-4484

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Abstract

In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors’s knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices.

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IITH Creators:

IITH Creators	ORCiD
Haldar, Arabinda	https://orcid.org/0000-0002-0490-9719
Murapaka, Chandrasekhar	UNSPECIFIED
Acharyya, Amit	http://orcid.org/0000-0002-5636-0676

Item Type:

Article

Uncontrolled Keywords:

3D low complex design; area efficient design; boolean optimization; nano architecture; runtime reconfigurability; skyrmion logic; Reconfigurable architectures; Computer circuits; Design; Logic gates; Magnetos; Tunnel junctions; 3d low complex design; Area efficient design; Area-Efficient; Boolean optimizations; Complex designs; Efficient designs; Nano-architecture; Runtime reconfigurability; Skyrmion logic; Skyrmions

Subjects:

Electrical Engineering
Electrical Engineering > Process Control
Physics
Physics > Modern physics
Materials Engineering > Testing and measurement
Materials Engineering > Materials engineering

Divisions:

Department of Electrical Engineering
Department of Material Science Engineering
Department of Physics

Depositing User:

Mr Nigam Prasad Bisoyi

Date Deposited:

27 Aug 2023 14:44

Last Modified:

27 Aug 2023 14:44

URI:

http://raiithold.iith.ac.in/id/eprint/11654