Low complex Hardware Architecture Design Methodology for Cubic Spline Interpolation Technique for Assistive Technologies

Cheduluri, Ganesh and Bhardwaj, Swati and Naik, Ganesh R and Hansigida, Vidhumouli and Nali, Appa Rao and Acharyya, Amit (2022) Low complex Hardware Architecture Design Methodology for Cubic Spline Interpolation Technique for Assistive Technologies. In: 20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022, 19 June 2022 through 22 June 2022, Quebec City.

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Abstract

The Hardware implementation of the Empirical mode decomposition algorithm has attracted attention in recent years due to its data-driven nature, adaptability, and ability to process non-stationary and non-linear signal analysis. Due to its high computation requirements for the sifting process, it is difficult to achieve low hardware complexity. The proposed design introduces an efficient VLSI architecture for the Cubic spline interpolation technique based on the Co-Ordinate Rotation Digital Computer(CORDIC) for generating envelops in the EMD algorithm. The design was implemented on Xilinx ZynqU ltraScale+ZCU 102 Evaluation Board and synthesized using Vivado 2018.1 Design Suite with the fixed-point data format and generated envelops using the sifting procedure. © 2022 IEEE.

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IITH Creators:

IITH Creators	ORCiD
Acharyya, Amit	http://orcid.org/0000-0002-5636-0676

Item Type:

Conference or Workshop Item (Paper)

Additional Information:

This work was partially supported by Xilinx INC USA and the Department of Science Technology(DST), Govt. of India.

Uncontrolled Keywords:

Co-ordinate Rotation Digital Computer(CORDIC); Cubic Spline Interpolation; Empirical Mode Decomposition; Intrinsic Mode Function; Surface EMG signal; Tridiagonal Matrix Algorithm

Subjects:

Electrical Engineering

Divisions:

Department of Electrical Engineering

Depositing User:

. LibTrainee 2021

Date Deposited:

08 Oct 2022 05:59

Last Modified:

08 Oct 2022 05:59

URI:

http://raiithold.iith.ac.in/id/eprint/10852