Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node

Sudarsanan, Akhil and Badami, Oves and Nayak, Kaushik (2021) Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node. In: 44th International Semiconductor Conference, CAS 2021, 6 October 2021through 8 October 2021, Virtual, Online.

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Abstract

The effect of interface trap variability (ITV) on horizontally stacked nanosheet FET (NSHFET) has been explored using TCAD based 3-D quantum corrected Drift-Diffusion simulation framework for sub-3 nm technology node. It is revealed that 3-stacked NSHFET shows 9.09% lesser VT variation compared to 3-stacked nanowire FET (NWFET) due to combined ITV sources such as charge neutrality level (CNL), single charged traps (SCTs), and random interface traps (RITs). The 3-stacked NSHFET and NWFET reduces the ITV induced VT variation by 31.3% and 28.8% respectively compared to the single stacked transistors. The NSHFETs of higher effective channel width shows better immunity to ITV. It is found that both Si NSHFET and NWFET transistors effectively suppresses the combined ITV sources induced VT, ION, and drain induced barrier lowering (DIBL) variations when the CNL is positioned between midgap and conduction band edge of the semiconductor bandgap. © 2021 IEEE.

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IITH Creators:

IITH Creators	ORCiD
Badami, Oves	UNSPECIFIED
Nayak, Kaushik	https://orcid.org/0000-0001-6583-264X

Item Type:

Conference or Workshop Item (Paper)

Additional Information:

The interface trap induced variability analysis of Si NSH-FET due to CNL, SCTs, and RITs have done for sub-3 nm logic nodes and compared with Si NWFET. The 3-stacked NSHFET shows less σVT (60%), less σION (69.2%), higher σIOFF(30.3%), high σSS (11.7%), and less σDIBL (67%) deviation as the CNL location shifts from EV to EC. The VT deviation of 3-stacked NSHFET due to combined ITV sources is decreased by 50%, 55.5%, and 55.5% for different channel widths (WSH) such as 25, 20, and 15 nm, respectively, as the CNL location shifts from EV to EC. The 3-stacked NSHFET shows lesser VT, ION, IOFF, and DIBL variation compared to the 3-stacked NWFET due to greater surface to volume ratio. Thus we conclude that 3-stacked Si NSHFET will be a better high-performance logic transistor for future sub-3nm technology node in terms of offering better immunity towards interface trap variability sources. ACKNOWLEDGMENT The authors would like to thank Electron Devices Research (EDR) laboratory of Electrical Engineering department of IIT Hyderabad for the valuable discussions and feedback. This research work has been supported by Visvesvaraya PhD Scheme, MeitY, Govt.of India,MEITY-PHD-853.

Uncontrolled Keywords:

CNL; ITV; NSHFET; NWFET; RIT; SCT

Subjects:

Electrical Engineering

Divisions:

Department of Electrical Engineering

Depositing User:

. LibTrainee 2021

Date Deposited:

01 Oct 2022 06:21

Last Modified:

01 Oct 2022 06:21